Two Ferro4EdgeAI partners have announced a close collaboration to develop FMC’s Cache+ chiplet, a low power high density alternative to standard SRAMs using 1T-1C FeRAMs with HfZrO2.

https://www.ferroelectric-memory.com/fmc-and-cea%e2%80%91leti-join-forces-to-advance-feram-cache-memory-for-the-ai-era/

CACHE+ reimagines SRAM, the high-speed CACHE used throughout computing. It delivers ten times the density of conventional SRAM while reducing standby power by a factor of ten. It also adds persistence, and is designed to integrate seamlessly with next-generation chiplet architectures for ultra-high-performance AI inference systems. Together, these capabilities unlock new possibilities for system designers who are rethinking architectures from the ground up. Crucial for AI data centers which cannot continue consuming power at their current trajectory.